The Advanced Encryption Standard (AES) is a FIPS-approved
cryptographic algorithm that can be used to protect electronic
data. The AES algorithm is a symmetric block cipher that can
encrypt (encipher) and decrypt (decipher) information. Encryption
converts data to an unintelligible form called ciphertext;
decrypting the ciphertext converts the data back into its
original form, called plaintext.
The AES algorithm is capable of using cryptographic keys of
128, 192, and 256 bits to encrypt and decrypt data in blocks
of 128 bits. Also, the AES algorithm is used in different
operation modes. The different modes include the Electronic
Code Book (ECB) mode, the Cipher Block Chaining (CBC) mode,
the Cipher Feed Back (CFB) mode, the Output Feed Back (OFB)
mode, and the Counter (CTR) mode. The CBC, CFB and OFB modes
have feedbacks and the ECB and CTR modes have no feedbacks.
Hence, full parallel implementation of the encryption/decryption
rounds will improve the data throughput of the ECB and CTR
The 3 Gbps AES core developed by Highland Communications
Technologies is fully compliant with the AES standard published in
FIPS PUB 197. It supports all the key lengths. The key expansion
unit is integrated in the core. The encryption and decryption is
run time programmable. Highland will custom design the wrapping
logic to support different operation modes for free.
The resource usage and performance parameters of the core are listed in table 1.
Table 1. Resource Usage And Performance Parameters For The 3 Gbps AES Core
|| CLB Slices
|| Block Ram
|| 18x18 Multipliers
|| Clock Speed
|| Data Throughput
| Virtex IV
|| 297 MHz
|| 3168 Mbps
Availability And Deliverables
The AES core is available now. Deliverables include source code in VHDL
or Verilog, netlist file for Xilinx and Altera FPGA, testbenches in VHDL
or Verilog, data Sheet and user guide.
Please use the following link to download the data sheet.
for more information.
3 Gbps AES Core