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16-Bit Parallel BCH(480, 444) Code

This is a 16-bit parallel BCH code. Both the encoder and the decoder take 16-bit parallel input and output 16-bit parallel output. The code length is 480. The data length is 444. The number of parity check bits is 36. The code can correct up to 4 error bits. Since the data length is not an integer multiple of 16, only the 12 MSBs of the last 16-bit data symbol are used as data input to the encoder. Both the encoder and the decoder use signle clock design. And both the encoder and the decoder support continuous operations.

Resource usage and performance parameters are listed in table 1 and table 2.

Table 1. Resource Usage And Performance Parameters For The BCH Encoder

Platform CLB Slices Block Ram 18x18 Multipliers Clock Speed
Virtex IV 274 0 0 208 MHz


Table 2. Resource Usage And Performance Parameters For The BCH Decoder

Platform CLB Slices Block Ram 18x18 Multipliers Clock Speed
Virtex IV 1714 1 0 243 MHz


Availability And Deliverables

The BCH code is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx or Altera FPGA, test benches in VHDL or Verilog.

Data Sheet

Please use the following link to down load the data sheet. Please contact us for more information.

16-Bit Parallel BCH(480,444) Encoder

16-Bit Parallel BCH(480,444) Decoder

 
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