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2.5 Gbps GPON (G.984) Reed-Solomon Code FREE Download For Verification

The GPON (G.984) Reed-Solomon code is fully compliant with the GPON (G.984) standard. It supports the upstream data rate of 2488.32 Mbps and 1244.16 Mbps and the downstream data rate of 2488.32 Mbps, 1244.16 Mbps, 622.08 Mbps, and 155.52 Mbps. It takes 8-bit, 16-bit, or 32-bit input to accormodate different date rates. Data block length can be any value from 1 to 65535. The last short code word is pre-zero padded according to the newly amended GPON standard and handled inside the codec for easy system integration. Error statistics include number of received bytes, number of corrected bytes, number of corrected bits, number of received codes and number of uncorrected codes. Resource usage and performance parameters are listed in Table 1 for the encoder and in Table 2 for the decoder.

Table 1. Resource Usage And Performance Parameters Of The Encoder

Product n, k, t Platform CLB Slices Block Ram Clock Speed Data Rate Latency
GPON Encoder Fixed n, k, t Virtex II 1232 8 187 MHz 5984 Mbps 198 Clock Cycle
Spartan III 1293 8 133 MHz 4256 Mbps 198 Clock Cycle


Table 2. Resource Usage And Performance Parameters Of The Decoder

Product n, k, t Platform CLB Slices Block Ram Clock Speed Data Rate Latency
GPON Decoder Fixed n, k, t Virtex II 4229 12 147 MHz 4704 Mbps 719 Clock Cycles
Spartan III 4409 12 111 MHz 3552 Mbps 719 Clock Cycles


Availability And Deliverables

The GPON(G.984) Reed-Solomon code is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification. Please contact us for more information.

Data Sheet

Please use the following link to download the data sheet.

2.5 Gbps GPON (G.984) FEC Encoder

2.5 Gbps GPON (G.984) FEC Decoder

FREE Download For Verification

We have designed a FREE testbench netlist for Xilinx Virtex II and Spartan III. It is a full version of the testbench, including the random number generator, the RS encoder, the RS decoder, and some control logic. An entity declaration in VHDL, a module declaration in Verilog, and a user guide are also included in the download files. You can use the following link to download the files and implement the testbench in your own hardware and verify the functionality and check the performance of our product. To use the free download files, you agree to be bound by this Term Of Use.

FREE Download For Virtex II

FREE Download For Spartan III

 
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