Reed-Solomon Code With (n, k) = (255, 239)

This is the most widely used Reed-Solomon code. Both the code length and the data length are fixed. The maximum number of correctable errors is 8. Resource usage and performance parameters are listed in Table 1 for the encoder and in Table 2 and Table 3 for the decoder. We have both a low gate count implementation and a low latency implementation of the decoder. The resource usage and performance parameters of the low gate count implementation of the decoder is listed in Table 2 and that of the low latency implementation of the decoder is listed in Table 3.

Table 1. Resource Usage And Performance Parameters Of The Encoder

Product	n, k, t	Platform	CLB Slices	Block Ram	Clock Speed	Data Rate	Latency
(255, 239) Encoder	Fixed n, k, t	Virtex II	156	0	200 MHz	1600 Mbps	1 Clock Cycle
		Spartan III	165	0	150 MHz	1200 Mbps	1 Clock Cycle

Table 2. Resource Usage And Performance Parameters Of The Decoder (Low Gate Count Implementation)

Product	n, k, t	Platform	CLB Slices	Block Ram	Clock Speed	Data Rate	Latency
(255, 239) Decoder	Fixed n, k, t	Virtex II	691	4	160 MHz	1280 Mbps	255 + 204 Clock Cycles
		Spartan III	699	4	140 MHz	1120 Mbps	255 + 204 Clock Cycles

Table 3. Resource Usage And Performance Parameters Of The Decoder (Low Latency Implementation)

Product	n, k, t	Platform	CLB Slices	Block Ram	Clock Speed	Data Rate	Latency
(255, 239) Decoder	Fixed n, k, t	Virtex II	1125	1	225 MHz	2000 Mbps	255 + 97 Clock Cycles
		Spartan III	1179	1	170 MHz	1360 Mbps	255 + 97 Clock Cycles

Availability And Deliverables

The Reed-Solomon code is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification. Please contact us for more information.

Data Sheet

Please use the following link to download the data sheet.

RS(255, 239) Encoder

RS(255, 239) Decoder