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RS(28, 24) with Erasures

For the RS(28, 24) code with erasure correction capability, the maximum number of correctable errors only is 2, and the maximum number of correctable erasures only is 4. When the number of erasures plus two times the number of errors is less than 4, both the errors and the erasures can be corrected. Resource usage and performance parameters for the encoder are listed in Table 1. Resource usage and performance parameters for the decoder are listed in Table 2.

Table 1. Resource Usage And Performance Parameters Of The Encoder

Product Platform CLB Slices Block Ram Clock Speed Data Rate Latency
RS(2, 24) Encoder Virtex IV 75 0 320 MHz 2400 Mbps 1 Clock Cycles


Table 2. Resource Usage And Performance Parameters Of The Decoder

Product Platform CLB Slices Block Ram Clock Speed Data Rate Latency
RS(28, 24) Decoder Virtex IV 933 1 219 MHz 1600 Mbps 28 + 28 Clock Cycles


Availability And Deliverables

The Reed-Solomon code is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx and Altera FPGAs, testbenches in VHDL or Verilog. Please contact us for more information.

Data Sheet

Please use the following link to download the data sheet.

RS(28, 24) Encoder

RS(28, 24) with Erasures Decoder

 
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