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The generator polynomial of the flexible (n, k) Reed-Solomon code can be configured on fly so that the maximum number of correctable errors of the code can be 1, 2, ..., 7, and 8. The code length and data length can take any value only if they satisfy the relationship n - k = 2 * t and n <= 255. Resource usage and performance parameters of the code are listed in Table 1 for the encoder and in Table 2 and Table 3 for the decoder. We have a low gate count implementation and a low latency implementation of the decoder. The resource usage and performance parameters of the low gate count implementation of the decoder is listed in Table 2 and that of the low latency implementation of the decoder is listed in Table 3.
Availability And Deliverables The Reed-Solomon code is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification. Please contact us for more information. Data Sheet Please use the following link to download the data sheet. Flexible Reed-Solomon Code Encoder Flexible Reed-Solomon Code Decoder FREE Download For Verification We have designed a FREE testbench netlist for Xilinx Virtex II and Spartan III. It is a full version of the testbench, including the random number generator, the RS encoder, the RS decoder, and some control logic. An entity declaration in VHDL, a module declaration in Verilog, and a user guide are also included in the download files. You can use the following link to download the files and implement the testbench in your own hardware and verify the functionality and check the performance of our product. To use the free download files, you agree to be bound by this Term Of Use. FREE Download For Virtex II FREE Download For Spartan III
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