Highland Communications Technologies

Reed-Solomon Code With Flexible (n, k)

The generator polynomial of the flexible (n, k) Reed-Solomon code can be configured on fly so that the maximum number of correctable errors of the code can be 1, 2, ..., 7, and 8. The code length and data length can take any value only if they satisfy the relationship n - k = 2 * t and n <= 255. Resource usage and performance parameters of the code are listed in Table 1 for the encoder and in Table 2 and Table 3 for the decoder. We have a low gate count implementation and a low latency implementation of the decoder. The resource usage and performance parameters of the low gate count implementation of the decoder is listed in Table 2 and that of the low latency implementation of the decoder is listed in Table 3.

Table 1. Resource Usage And Performance Parameters Of The Encoder

Product	n, k, t	Platform	CLB Slices	Block Ram	Clock Speed	Data Rate	Latency
Flexible Encoder	Flexible n, k, t = 1, 2, ..., 8	Virtex II	642	0	90 MHz	720 Mbps	1 Clock Cycle
Flexible Encoder	Flexible n, k, t = 1, 2, ..., 8	Spartan III	631	0	87.5 MHz	700 Mbps	1 Clock Cycle

Table 2. Resource Usage And Performance Parameters Of The Decoder (Low Gate Count Implementation)

Product	n, k, t	Platform	CLB Slices	Block Ram	Clock Speed	Data Rate	Latency
Flexible Decoder	Flexible n, k, t = 1, 2, ..., 8	Virtex II	1161	4	140 MHz	1120 Mbps	n + 2 * (t^2) + 8 * t + 12 Clock Cycles
Flexible Decoder	Flexible n, k, t = 1, 2, ..., 8	Spartan III	1172	4	120 MHz	960 Mbps	n + 2 * (t^2) + 8 * t + 12 Clock Cycles

Table 2. Resource Usage And Performance Parameters Of The Decoder (Low Latency Implementation)

Product	n, k, t	Platform	CLB Slices	Block Ram	Clock Speed	Data Rate	Latency
Flexible Decoder	Flexible n, k, t = 1, 2, ..., 8	Virtex II	1581	1	100 MHz	800 Mbps	n + 11 * t + 9 Clock Cycles
Flexible Decoder	Flexible n, k, t = 1, 2, ..., 8	Spartan III	1561	1	100 MHz	800 Mbps	n + 11 * t + 9 Clock Cycles

Availability And Deliverables

The Reed-Solomon code is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification. Please contact us for more information.

Data Sheet

Please use the following link to download the data sheet.

Flexible Reed-Solomon Code Encoder

Flexible Reed-Solomon Code Decoder

FREE Download For Verification

We have designed a FREE testbench netlist for Xilinx Virtex II and Spartan III. It is a full version of the testbench, including the random number generator, the RS encoder, the RS decoder, and some control logic. An entity declaration in VHDL, a module declaration in Verilog, and a user guide are also included in the download files. You can use the following link to download the files and implement the testbench in your own hardware and verify the functionality and check the performance of our product. To use the free download files, you agree to be bound by this Term Of Use.

FREE Download For Virtex II

FREE Download For Spartan III