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Reed-Solomon Code With Fixed t = 8

The generator polynomial of the Reed-Solomon code is fixed such that the maximum number of correctable errors of the code is 8. The code length and data length can take any value only if they satisfy the relationship n - k = 2 * 8 and n <= 255. Resource usage and performance parameters of the code are listed in Table 1 for the encoder and in Table 2 and Table 3 for the decoder. We have a low gate count implementation and a low latency implementation of the decoder. The resource usage and performance parameters of the low gate count implementation of the decoder is listed in Table 2 and that of the low latency implementation of the decoder is listed in Table 3.

Table 1. Resource Usage And Performance Parameters Of The Encoder

Product n, k, t Platform CLB Slices Block Ram Clock Speed Data Rate Latency
t = 8 Encoder Flexible n, k, t = 8 Virtex II 155 0 125 MHz 1000 Mbps 1 Clock Cycle
Spartan III 163 0 125 MHz 1000 Mbps 1 Clock Cycle


Table 2. Resource Usage And Performance Parameters Of The Decoder (Low Gate Count Implementation)

Product n, k, t Platform CLB Slices Block Ram Clock Speed Data Rate Latency
t = 8 Decoder Flexible n, k, t = 8 Virtex II 1161 4 140 MHz 1120 Mbps n + 204 Clock Cycles
Spartan III 1172 4 120 MHz 960 Mbps n + 204 Clock Cycles


Table 3. Resource Usage And Performance Parameters Of The Decoder (Low Latency Implementation)

Product n, k, t Platform CLB Slices Block Ram Clock Speed Data Rate Latency
t = 8 Decoder Flexible n, k, t = 8 Virtex II 1581 1 100 MHz 800 Mbps n + 97 Clock Cycles
Spartan III 1561 1 100 MHz 800 Mbps n + 97 Clock Cycles


Availability And Deliverables

The Reed-Solomon code is available now. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification. Please contact us for more information.

Data Sheet

Please use the following link to down load the data sheet.

T = 8 RS Code Encoder

T = 8 RS Code Decoder

 
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