Rate 1/2 Turbo Convolutional Code For 802.16d
The Turbo convolutional code for 802.16d uses two parallel concatenated Double Binary
Circular Recursive Systematic Convolutional Codes (DBCRSCC) as constituent codes.
The advantages of DBCRSCC includ better convergence and better performance, especially
with short code at high SNR and high code rate, than a single binary Turbo convolutional
code. The error floor of the code is so low that quasi error free decoding is possible
with limitted number of iterations. The circular state transition property eliminates
the need for tail ending data and hence achieving higher data rate than a single binary
Turbo convolutional code.
There are two basic Turbo Convolutional codes defined in the 802.16d standard, namely
a rate 1/2 code and a rate 1/3 code. Codes with different code rates are derived from
the basic codes through parity puncturing. The rate 1/2 and the rate 1/3 code implemented
by HLCT is fully compliant with the 802.16d standard. System designers can use different
puncturing schemes based on their system requirements to get different code rates.
The resource usage and performance parameters of the rate 1/2 Turbo Convolutional Code
are listed in Table 1 for the encoder and in Table 2 for the decoder. The bit error
rate performance of the code with a 240-couple data block is shown in Figure 1.
It can be seen that while each iteration will improve the performance of
the code, the fourth iteration doesn't improve the performance as much as the first
few ones. Another observation is that with such a short data block there is no error
floor observed at 10^7 bit error rate.
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Table 1. Resource Usage And Performance Parameters For The TCC Encoder
|
| Platform |
CLB Slices |
Block Ram |
18x18 Multipliers |
Clock Speed |
| Virtex IV |
559 |
2 |
1 |
177 MHz |
|
Table 2. Resource Usage And Performance Parameters For The TCC Decoder
|
| Platform |
CLB Slices |
Block Ram |
18x18 Multipliers |
Clock Speed |
Data Rate |
Input Resolution |
| Virtex IV |
5324 |
19 |
1 |
152 MHz |
65 - 145 Mbps |
4 bit |
|
Figure 1. The bit error rate performance of the rate 1/2 Turbo Convolotional Code
for 802.16d/e with different number of iterations. The data length is 240 couples.
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Availability And Deliverables
The rate 1/2 Turbo Convolutional Code for 802.16d is available now.
Deliverables include source code in VHDL
or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog,
and C/C++ source code for modeling and verification.
Data Sheet
Please use the following link to down load the data sheet.
Please
contact us
for more information.
Rate 1/2 802.16d Turbo Convolutional Code Encoder
Rate 1/2 802.16d Turbo Convolutional Code Decoder
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