The Turbo convolutional code for 3GPP2 is fully compliant with the 3GPP2 specification.
It supports all the code rates and all the data block lengths. The maximum data rate
can be 2 Mbps at 8 iterations or 4 Mbps at 4 iterations. It takes 4 bit soft input for
both the data and the parity symbols. The early termination mechanism can stop the
decoding process once the optimal performance is achieved. There is no need for external
noise power estimation. The compact design makes it one of the smallest Turbo Convolutional
Code on the market.
The resource usage and performance parameters are listed in Table 1 for the TCC
encoder and Table 2 for the TCC decoder. The bit error rate performance of the
implementation is shown in Figure 1 and Figure 2. Figure 1 shows the bit error
rate performance of a length 6138, rate 1/4 code with different number of iterations.
It can be seen that while each iteration improves the performance of the code, the
fifth iteration doesn't improve the performance as much as the first few ones. In
addition, when the BER reaches 10^(-7), the error floor of the code starts to show
itself. The error floor of the 3GPP code could be lower than that of the 3GPP2 code
becuse of the more complex interleaving algorithm. Figure 2 shows the bit error rate
performance of the code with different code rates. The code length is 378 and the
number of iterations is 1. It can be seen that when the code rate changes from 1/2
to 1/3, the BER performance of the code improves about 0.5 dB. However, when then
code rate changes from 1/3 to 1/4, the improvement of the BER performance is trivial.
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Table 1. Resource Usage And Performance Parameters For The TCC Encoder
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| Platform |
CLB Slices |
Block Ram |
18x18 Multipliers |
Clock Speed |
| Virtex II |
271 |
12 |
1 |
75 MHz |
| Spartan III |
253 |
12 |
1 |
65 MHz |
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Table 2. Resource Usage And Performance Parameters For The TCC Decoder
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| Platform |
CLB Slices |
Block Ram |
18x18 Multipliers |
Clock Speed |
Data Rate |
Sliding Window Length |
Input Resolution |
| Virtex II |
1608 |
57 |
1 |
75 MHz |
2 Mbps (8 Iters) 4 Mbps (4 Iters) |
40 |
4 bit |
| Spartan III |
1671 |
57 |
1 |
60 MHz |
2 Mbps (6 Iters) 4 Mbps (3 Iters) |
40 |
4 bit |
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Figure 1. The bit error rate performance of the Turbo Convolotional Code for 3GPP2
with different number of iterations. The code rate is 1/4. The data length is 6138.
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Figure 2. The bit error rate performance of the Turbo Convolotional Code for 3GPP2
with different code rates. The data length is 378. The number of iteration is 1.
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Availability And Deliverables
The Turbo Convolutional Code for 3GPP2 is available now. Deliverables include source code in VHDL
or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source
code for modeling and verification.
Data Sheet
Please use the following link to down load the data sheet.
Please
contact us
for more information.
3GPP2 Turbo Convolutional Code Encoder
3GPP2 Turbo Convolutional Code Decoder
FREE DownLoad For Verification
We have designed a FREE testbench netlist for Xilinx Virtex II and Spartan III. It is a full
version of the testbench, including the random number generator, the TCC encoder, the TCC decoder,
and some control logic. An entity declaration in VHDL, a module declaration in Verilog, and
a user guide are also included in the download files. You can use the following link to
download the files and implement the testbench in your own hardware and verify the functionality
and check the performance of our product. To use the free download files, you agree to be bound
by this
Term Of Use.
FREE Download For Virtex II
FREE Download For Spartan III
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