Turbo Convolutional Code For DVB_RCS

The Turbo convolutional code for DVB-RCS uses two parallel concatenated Double Binary Circular Recursive Systematic Convolutional Codes (DBCRSCC) as constituent codes. The advantages of DBCRSCC includ better convergence and better performance, especially at high SNR and high code rate, than a single binary Turbo convolutional code. The error floor of the code is so low that quasi error free decoding is possible with limitted number of iterations. The circular state transition property eliminates the need for tail ending data and hence achieving higher data rate than a single binary Turbo convolutional code.

The HLCT implementation of the DVB-RCS TCC is fully compliant with the standard. It supports data blocks of 12, 16, 53, 55, 57, 106, 108, 110, 188, 212, 214 and 216 bytes and code rates of 1/3, 2/5, 1/2, 2/3, 3/4, 4/5 and 6/7. It takes 4 bit soft input for both the data and the parity symbols and there is no need for external noise power estimation. The encoder uses approximately 400 Virtex-II CLB slices, 1 Virtex-II 18x18 multiplier and 2 Virtex-II Block Rams. The throughput of the encoder is around 60 Mbps for a rate 1/2 code. The decoder uses approximately 2000 Virtex-II CLB slices, 1 Virtex-II 18x18 multiplier and 8 Virtex-II Block Rams. The data through put is 6 Mbps for 12-byte data blocks and 11 Mbps for 216-byte data blocks for a rate 1/2 code at 4 iterations.

Availability And Deliverables

The Turbo Convolutional Code for DVB-RCS will be available soon. Deliverables include source code in VHDL or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and C/C++ source code for modeling and verification.

Data Sheet

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