|
Viterbi decoder is the maximum likelihood sequence decoder
for a convolutional code. In this IP core the encoder
is the industry standard convolutional code of code rate
R = 1/2, constraint length K = 7 and generator polynomials
G0 = 133 and G1 = 171. The decoder is a soft input high
throughput Viterbi decoder.
The Viterbi decoder has three functional units: the Branch
Metric Unit, the Add Compare Select Unit, and the Trace Back
Unit. The Branch Metric Unit calculates the four possible
branch metrics based on the input symbol and the Add Compare
Select Unit generates the trellis diagram. The Trace Back Unit
starts from state 0 to trace back a certain amount of stages
on the Trellis diagram. At the end of the trace back all the
paths are supposed to have converged to the correct path. The
decision bit at the end of the trace back path is the decoded
data bit.
Resource usage and performance parameters are listed in table 1.
|
Table 1. Resource Usage And Performance Parameters
|
| Platform |
CLB Slices |
Block Ram |
Clock Speed |
Data Rate |
Trace Back Length |
Latency |
Input Resolution |
| Virtex II |
1168 |
4 |
122 MHz |
122 Mbps |
64 Stages |
267 Clock Cycles |
4 bit |
| Spartan III |
1236 |
4 |
108 MHz |
108 Mbps |
64 Stages |
267 Clock Cycles |
4 bit |
Availability And Deliverables
The Viterbi decoder is available now. Deliverables include source code in VHDL
or Verilog, netlist file for Xilinx FPGA, testbenches in VHDL or Verilog, and
C/C++ source code for modeling and verification.
Data Sheet
Please use the following link to down load the data sheet.
Please
contact us
for more information.
Viterbi Decoder
|
